A state assignment approach to asynchronous CMOS circuit design

Author

Kantabutra, Vitit ; Andreou, Andreas G.

Author_Institution

Dept. of Comput. Sci., State Univ. of New York, Brockport, NY, USA

Volume

43

Issue

4

fYear

1994

fDate

4/1/1994 12:00:00 AM

Firstpage

460

Lastpage

469

Abstract

Present a new algorithm for state assignment in asynchronous circuits so that for each circuit state transition, only one (secondary) state variable switches. No intermediate unstable states are used. The resultant circuits operate at optimum speed in terms of the number of transitions made and use only static CMOS gates. By reducing the number of switching events per state transition, noise due to the switching events is reduced and dynamic power dissipation may also be reduced. This approach is suitable for asynchronous sequential circuits that are designed from flow tables or state transition diagrams. The proposed approach may also be useful for designing synchronous circuits, but explorations into the subject of clock power would be necessary to determine its usefulness

Keywords

CMOS integrated circuits; asynchronous sequential logic; integrated logic circuits; logic design; sequential circuits; state assignment; CMOS gates; asynchronous CMOS circuit design; asynchronous circuits; asynchronous sequential circuits; flow tables; state assignment; state transition diagrams; switching events; Asynchronous circuits; Circuit noise; Circuit synthesis; Noise reduction; Power dissipation; Power supplies; Sequential circuits; Switches; Switching circuits; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.278483

Filename

278483