A vertical FET with self-aligned ion-implanted source and gate regions

A new self-aligned vertical channel JFET has been fabricated using ion-implantation and LOCOS techniques. This device required four photolithography processes. Fine patterning and accurate mask alignment are not required by this process. The electrical properties of this device are a voltage amplification factor of more than 5, a source-to-gate breakdown voltage of 50 V, and a drain-to-gate breakdown voltage of 140 V. It is possible to realize a larger voltage amplification factor, compared to the diffused vertical FET.