A Low Complexity Geometric Mean Decomposition Computing Scheme and Its High Throughput VLSI Implementation

Geometric Mean Decomposition (GMD) is considered an efficient precoding scheme in joint MIMO transceiver designs capable of facilitating asymptotically equivalent performance of maximum likelihood detector (MLD). In this paper, a low complexity and non-iterative GMD computing scheme featuring a divide-and-conquer approach is presented. It requires no iterative singular value decomposition (SVD) as pre-processing and is thus exempted from the convergence problem adverse to a constant throughput hardware implementation. The divide-and-conquer approach reduces the computing complexity and provides abundant computing parallelism. The basic operation of the proposed scheme is a real valued Givens rotation, which can be efficiently implemented using CORDIC algorithm. Computing complexity analyses indicate that the proposed scheme is at least 30% more computing efficient than other SVD based GMD computing schemes. Finally, a unified GMD/QRD design using a fully parallel and deeply pipelined architecture is presented. One GMD or QRD computation on a 4x4 complex-valued matrix can be accomplished every 4 clock cycles. Chip implementation in TSMC 90 nm CMOS technology shows that, with a maximum clock frequency up to 170 MHz, the design can perform 42.5 M GMD computations per second. The equivalent data rate is 1.02 Gbps for a 64 QAM modulation scheme.