Multi- ${\rm J}_{\rm c}$ (Josephson Critical Current Density) Process for Superconductor Integrated Circuits

Many applications of superconductor integrated circuits may require a small part of the circuit to work at the highest possible clock frequency, e.g. an ADC in the receiver front-end, while more complex parts of the circuits may work at a lower frequency, e.g. a digital filter. Since the maximum clock frequency is proportional to the square root of the Josephson critical current density (J_c), such circuits can be realized as multi-J_c circuits containing trilayers with different J_c´s. A fabrication technology will be presented enabling a single chip to accommodate circuits optimized for different critical current densities. Details of the multi-J_c process will be discussed as well as the typical circuit implementations and test results.