DocumentCode
1060388
Title
Defect or Variation? Characterizing Standard Cell Behavior at 90 nm and Below
Author
Aitken, Robert C.
Author_Institution
ARM, Inc., Sunnyvale
Volume
21
Issue
1
fYear
2008
Firstpage
46
Lastpage
54
Abstract
Historically, design margin and defects have been viewed as different topics, one a part of design and the other a part of a test. Shrinking process geometries are making the two part of a continuum. This paper discusses the leakage and delay behavior associated with classic resistive defects and compares it with transistor variation due to lithography.
Keywords
delays; design for testability; integrated circuit design; leakage currents; nanolithography; delay behavior; design margin; leakage bahavior; lithography process; resistive defects; shrinking process geometries; standard cell behavior; transistor variation; Circuit faults; Circuit testing; Delay; Design for testability; Geometry; History; Lithography; Manufacturing; Threshold voltage; Transistors; Characterization; defect modeling; design margin; standard cells; variation;
fLanguage
English
Journal_Title
Semiconductor Manufacturing, IEEE Transactions on
Publisher
ieee
ISSN
0894-6507
Type
jour
DOI
10.1109/TSM.2007.913191
Filename
4447296
Link To Document