A Low-Power Low-VDD Nonvolatile Latch Using Spin Transfer Torque MRAM

The high leakage power due to the scaling down of the process nodes has been one of the critical issues in CMOS circuits, especially in the sleep power critical systems. The emerging nonvolatile flip-flops (nvFFs) with fast saving and restoration speed and zero sleep power may be the solution to address the high sleep power issue. However, the “source degeneration” and/or “serial write” issues of the reported works may significantly limit the scalability. We propose a novel nvFF using two-phase write approach and complementary write drivers, which reduces more than 38% power for the saving operation and also scales VDD down to 1 V and below. Our proposed nvFF has the closest flip-flop (FF) performance as the CMOS retention FF. Moreover, it has more than 50% area reduction compared to the smallest nvFF in the prior arts.