DocumentCode :
1060708
Title :
SOS wafers—Some comparisons to silicon wafers
Author :
Maurits, Jan E A
Author_Institution :
Union Carbide Corporation, San Diego, CA
Volume :
25
Issue :
8
fYear :
1978
fDate :
8/1/1978 12:00:00 AM
Firstpage :
859
Lastpage :
863
Abstract :
Some comparisons between SOS wafers and silicon wafers used in the processing of MOS integrated circuits are presented. These comparisons are useful in understanding the differences in handling techniques, specifications, and costs; as well as identifying areas of future material quality improvement and cost reduction programs. Growth conditions, material quality, geometric dimensions, epitaxial-film deposition conditions, and evaluation techniques are compared.
Keywords :
Costs; Crystalline materials; Furnaces; Lattices; MOS integrated circuits; Semiconductor impurities; Silicon; Substrates; Temperature; Thermal resistance;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1978.19191
Filename :
1479585
Link To Document :
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