Title :
SOS wafers—Some comparisons to silicon wafers
Author :
Maurits, Jan E A
Author_Institution :
Union Carbide Corporation, San Diego, CA
fDate :
8/1/1978 12:00:00 AM
Abstract :
Some comparisons between SOS wafers and silicon wafers used in the processing of MOS integrated circuits are presented. These comparisons are useful in understanding the differences in handling techniques, specifications, and costs; as well as identifying areas of future material quality improvement and cost reduction programs. Growth conditions, material quality, geometric dimensions, epitaxial-film deposition conditions, and evaluation techniques are compared.
Keywords :
Costs; Crystalline materials; Furnaces; Lattices; MOS integrated circuits; Semiconductor impurities; Silicon; Substrates; Temperature; Thermal resistance;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1978.19191