DocumentCode
1060741
Title
The use of a silicon-gate C-MOS/SOS test vehicle to evaluate technology maturity
Author
Jerdonek, Ronald T. ; Bare, Harold F., Jr. ; Fromen, Gregory J.
Author_Institution
U.S. Department of Defense, Ft. George G. Meade, MD
Volume
25
Issue
8
fYear
1978
fDate
8/1/1978 12:00:00 AM
Firstpage
873
Lastpage
878
Abstract
This paper describes a comprehensive test vehicle that has been used to characterize the silicon-gate C-MOS/SOS technology. Specifically, it has facilitated the verification of a set of topological layout rules and mask sequence which are producible industry-wide; the establishment of electrical design parameters; and has provided information on the present yield and performance range of the technology. In addition, structures included on the vehicle make it suitable for process development.
Keywords
Circuit testing; Costs; Defense industry; Epitaxial layers; Ion implantation; Life testing; Paper technology; Silicon; Substrates; Vehicles;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1978.19194
Filename
1479588
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