A 2-µm silicon-gate C-MOS/SOS technology

A 2-µm silicon gate deep-depletion C-MOS/SOS technology is described and characterized. The fabrication technology features all dry processing (ion milling and plasma etching) ion implanted source and drain, 2-µm features on all levels, phosphorous glass reflow for improved yield, and low-temperature processing (T ≤ 875°C). Characterization of the static electrical parameters as a function of channel length is presented. Circuit performance was characterized using a ring oscillator and a pattern generator. The ring oscillator exhibited stage delay as small as 220 ps at 5 V and an associated speed power product of less than 5 pJ. The pattern generator achieved an 80-MHz data rate. The potential of this technology for extension to submicrometer geometries was demonstrated by fabrication of discrete transistors with O.5-µm channel lengths.