Title :
TA-A1 VLSI limitations from drain-induced barrier-lowering
fDate :
11/1/1978 12:00:00 AM
Keywords :
Capacitors; Circuit simulation; Coupling circuits; Doping; FETs; Numerical models; P-n junctions; Semiconductor process modeling; Very large scale integration; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1978.19300
