Title :
Double-level metallurgy defect study
Author :
Gregoritsch, A.J., Jr.
Author_Institution :
IBM General Technology Division, Essex Junction, VT
fDate :
1/1/1979 12:00:00 AM
Abstract :
A double-level metallurgy (DLM) test chip having purposely induced nonrandom quartz insulation defects (cracks and holes) is used to study the behavior of the defects under accelerated temperature-voltage stress conditions. Data obtained from this stress are analyzed and used to calculate activation energies for an Arrhenius-voltage dependent model.
Keywords :
Acceleration; Insulation testing; Integrated circuit technology; Life estimation; Sputter etching; Stress; Surface cracks; Temperature dependence; Vehicles; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1979.19375
