System in Package (SiP) With Reduced Parasitic Inductance for Future Voltage Regulator

Author

Hashimoto, Takayuki ; Shiraishi, Masaki ; Akiyama, Noboru ; Kawashima, Tetsuya ; Uno, Tomoaki ; Matsuura, Nobuyoshi

Author_Institution

Hitachi Res. Lab., Hitachi, Ltd., Hitachi

Volume

24

Issue

6

fYear

2009

fDate

6/1/2009 12:00:00 AM

Firstpage

1547

Lastpage

1553

Abstract

A system in package (SiP) that integrates high-side and low-side MOSFETs and their driver IC has been developed for voltage regulators. Compared with the conventional discrete package, the SiP offers 25% lower power loss because it has low parasitic inductances. The peak drain voltage of the low-side MOSFET during turn- on of the high-side MOSFET is 45% lower than that of the discrete package, and this improves switching noise characteristics and lowers MOSFET conduction losses because it decreases the MOSFET breakdown voltage. A mixed-mode simulation was performed that indicated the common-source parasitic inductance should be reduced in order to attain low switching loss. To reduce this common-source parasitic inductance, the source pad of the high-side MOSFET is bonded directly to the driver IC with a wire.

Keywords

MOSFET; mixed analogue-digital integrated circuits; system-in-package; voltage regulators; MOSFET breakdown voltage; common-source parasitic inductance; drain voltage; driver IC; future voltage regulator; low-side MOSFETs; mixed-mode simulation; parasitic inductances; power loss; switching noise characteristics; system-in-package; Capacitors; Inductance; MOSFET circuits; Microprocessors; Packaging; Regulators; Switching frequency; Switching loss; Virtual reality; Voltage; Low parasitic inductance; packaging; power FETs; voltage regulator (VR);

fLanguage

English

Journal_Title

Power Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0885-8993

Type

jour

DOI

10.1109/TPEL.2009.2013225

Filename

5067411