LSI´s for digital signal processing

This paper describes high-performance CMOS LSI´s for digital signal-processing (DSP) technology, such as digital filter, fast Fourier transform (FFT), discrete Fourier transform (DFT), and digital phase-locked loop (DPLL). First, DSP functions for communication use, functional blocks to compose DSP functions, and the types of arithmetic for LSI are discussed. It is explained that multiplier (MPL), variable-length shift register (VSR), and linear arithmetic processor (LAP) have been chosen as the most useful DSP LSI´s. Device design for high-speed and low-power CMOS is described and its feasibility is shown as characteristics of propagation delay time at 430 ps and power delay product at 0.073 pJ. The 3-µm effective channel-length CMOS technology has been selected for the DSP LSI because of the high speed, 5 ns, in the case of two input NAND gates and high yield technology. The multiplier architecture is pipeline and uses the Two´s-complement representative, the variable-length shift register uses the binary-select method, and the linear arithmetic processor uses the method of changing the outside connections for realization of DSP functions. Maximum operating frequency of these LSI´s is more than 23 MHz at the 5-V source voltage. Power dissipation of a VSR, which has been lossy, is less than 250 mW in the 8-MHz operation. They have wider application to communication systems. High-speed CMOS technology is applied to the digital system equipment up to the second level of the PCM hierarchy.