• DocumentCode
    1063219
  • Title

    1 µm MOSFET VLSI technology: Part IV—Hot-electron design constraints

  • Author

    Ning, Tak H. ; Cook, Peter W. ; Dennard, Robert H. ; Osburn, Carlton M. ; Schuster, Stanley E. ; Yu, Hwa-Niew

  • Author_Institution
    IBM Thomas J. Watson Research Center, Yorktown Heights, NY
  • Volume
    26
  • Issue
    4
  • fYear
    1979
  • fDate
    4/1/1979 12:00:00 AM
  • Firstpage
    346
  • Lastpage
    353
  • Abstract
    An approach is described for determining the hot-electron-limited voltages for silicon MOSFET\´s of small dimensions. The approach was followed in determining the room-temperature and the 77 K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 µm. The substrate hot-electron limits were determined empirically from measurements of the emission probabilities as a function of voltage using devices of reentrant geometry. The channel hot-electron limits were determined empirically from measurements of the injection current as a function of voltage and from long-term stress experiments. For the 1 µm design considered, the channel hot-electron limits are lower than the substrate hot-electron limits. The maximum voltage, V_{DS} = V_{GS} , is 4.75 V at room temperature (25°C) and 3.5 V at 77 K. More details of the voltage limits as well as the approach for determining them are discussed. Examples of circuits designed with these devices to operate within these hot-electron voltage limits are also discussed.
  • Keywords
    Current measurement; Electron traps; Insulation; Leakage current; MOSFET circuits; Silicon; Stress measurement; Substrate hot electron injection; Very large scale integration; Voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1979.19433
  • Filename
    1480011