DocumentCode :
1063558
Title :
A new fabrication method of small-dimension devices—Multiple-wall self-aligned devices
Author :
Shibata, Hiroshi ; Iwasaki, Hideo ; Yamada, Kunic ; Oku, Taiji ; Tarui, Yasuo
Author_Institution :
VLSI Technology Research Association, Kawasaki-shi, Japan
Volume :
26
Issue :
4
fYear :
1979
fDate :
4/1/1979 12:00:00 AM
Firstpage :
604
Lastpage :
610
Abstract :
The fabrication procedure and device characteristics of the multiple-wall self-aligned devices are described. Two neighboring resist walls are photolithographed on a silicon wafer to protect the intervening region between the walls from diagonal incident ion beams. By using this shadowing effect in ion-beam etching and the ion implantation, only one photomask or one electron-beam exposure is required to fabricate the major components of MOSFET´s or bipolar transistors. The results of performance testing of MOS and bipolar transistors fabricated with this process are presented.
Keywords :
Bipolar transistors; Etching; Fabrication; Ion beams; Ion implantation; Protection; Resists; Shadow mapping; Silicon; Testing;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1979.19466
Filename :
1480044
Link To Document :
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