Title :
The effect of drain offset on current-voltage characteristics in sub micron polysilicon thin-film transistors
Author :
Olasupo, K.R. ; Yarbrough, W. ; Hatalis, M.K.
Author_Institution :
AT&T Bell Labs., Allentown, PA, USA
fDate :
8/1/1996 12:00:00 AM
Abstract :
We have examined the effect of drain offset structures with lengths ranging from 0.0 μm to 1.0 μm on submicron polysilicon TFT devices. The drain offset was found to exhibit resistive behavior that tends to lower the TFT drive current as it reduces the leakage current. For the range of channel lengths studied (1.0 μm to 0.35 μm) the optimum drain offset length was 0.35 μm
Keywords :
characteristics measurement; elemental semiconductors; leakage currents; silicon; thin film transistors; 0.0 to 1.0 micron; 1.0 to 0.35 micron; Si; channel lengths; current-voltage characteristics; drain offset; leakage current; resistive behavior; sub micron polysilicon thin-film transistors; Active matrix liquid crystal displays; Computer science; Doping; Flexible printed circuits; Leakage current; Silicon; Substrates; Thin film devices; Thin film transistors; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
