Architectures and VLSI implementations of the AES-Proposal Rijndael

Author

Sklavos, N. ; Koufopavlou, O.

Author_Institution

Electr. & Comput. Eng. Dept., Patras Univ., Greece

Volume

51

Issue

12

fYear

2002

fDate

12/1/2002 12:00:00 AM

Firstpage

1454

Lastpage

1459

Abstract

Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decryption process. They reduce the required hardware resources and achieve high-speed performance. Their design philosophy is completely different. The first uses feedback logic and reaches a throughput value equal to 259 Mbit/sec. It performs efficiently in applications with low covered area resources. The second architecture is optimized for high-speed performance using pipelined technique. Its throughput can reach 3.65 Gbit/sec.

Keywords

VLSI; cryptography; pipeline processing; transport protocols; AES-Proposal Rijndael; VLSI implementations; decryption process; encryption; feedback logic; hardware resources; pipelined technique; pipelining architectures; secure transport protocols; Algorithm design and analysis; Cryptography; Feedback; Field programmable gate arrays; Hardware; NIST; Proposals; Resource management; Throughput; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/TC.2002.1146712

Filename

1146712