DocumentCode :
1063844
Title :
Transferred-electron logic gates
Author :
Curtice, Walter R.
Author_Institution :
RCA Laboratories, Princeton, NJ
Volume :
26
Issue :
5
fYear :
1979
fDate :
5/1/1979 12:00:00 AM
Firstpage :
780
Lastpage :
786
Abstract :
A two-dimensional modeling technique is used to simulate GaAs transferred-electron devices operated as a logic gate (the TELD) and as a threshold gate. The simple logic gate has a good transfer characteristic but is shown sensitive to bias variations and operates with monostable output. For an input logic swing of 0.6 V and a fanout of 2, a propagation delay of 26 ps and gain of 1.25 is predicted. A bi-stable threshold gate shows a turn-on time of about 80 ps. An FET-triggered two-terminal transferred-electron device is calculated to have propagation delay of 27 ps with a gain of -1.2. Subsequent similar stages would require a noninverted output obtainable from a capacitive electrode on the TED. However, it is shown that additional anode load resistance is required to obtain a significant positive pulse output from such capacitive electrodes. The bias power requirement is estimated to be similar to the simple TELD gate.
Keywords :
Boundary conditions; Circuits; Electrodes; Gallium arsenide; Geometry; Logic devices; Logic gates; Microcomputers; Poisson equations; Propagation delay;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1979.19493
Filename :
1480071
Link To Document :
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