DocumentCode
1064001
Title
A fault-tolerant 64K dynamic random-access memory
Author
Cenker, Ronald P. ; Clemons, Donald G. ; Huber, William R. ; Petrizzi, Joseph B. ; Procyk, Frank J. ; Trout, George M.
Author_Institution
Bell Laboratories, Inc., Allentown, PA
Volume
26
Issue
6
fYear
1979
fDate
6/1/1979 12:00:00 AM
Firstpage
853
Lastpage
860
Abstract
A 64K dynamic MOS RAM with features and performance fully compatible with current 16K RAM´s has been designed and characterized. The memory cell is a one-transistor-one-capacitor structure, standard except for a polysilicon bit line. A dual-32K architecture, along with partial selection and stepped recovery, holds power and peak current values below those of 16K parts. Spare rows and columns, which can be substituted for defective elements by the laser opening of polysilicon links, enhance yield. Worst case column enable access time of the memory is 100 ns, row enable access time is 170 ns, and only 128 cycles within 4 ms are needed to refresh the device.
Keywords
Availability; Chip scale packaging; Circuits; Clocks; Costs; DRAM chips; Decoding; Fault tolerance; Random access memory; Read-write memory;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1979.19509
Filename
1480087
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