DocumentCode
1064035
Title
A high-speed low-power Hi-CMOS 4K static RAM
Author
Minato, Osamu ; Masuhara, Toshiaki ; Sasaki, Toshio ; Sakai, Yoshio ; Kubo, Masaharu ; Uchibori, K. ; Yasui, T.
Author_Institution
Hitachi Central Research Laboratory, Tokyo, Japan
Volume
26
Issue
6
fYear
1979
fDate
6/1/1979 12:00:00 AM
Firstpage
882
Lastpage
885
Abstract
A high-speed low-power CMOS fully static, 4096 word by 1 bit random-access memory (RAM) has been developed, which contains a bipolar-CMOS (BCMOS) circuit on the same chip. The device is realized using low-power-oriented circuit design and high-performance CMOS technology utilizing 3-µm gate length. The fabricated 4K static RAM has an address access time of 43 ns and a power dissipation of 80 mW.
Keywords
CMOS logic circuits; CMOS memory circuits; CMOS technology; Circuit synthesis; MOS devices; Power dissipation; Random access memory; Read-write memory; Switching circuits; Voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1979.19513
Filename
1480091
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