Title :
Probabilistic delay budget assignment for synthesis of soft real-time applications
Author :
Ghiasi, Soheil ; Huang, Po-Kuan ; Jafari, Roozbeh
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA
Abstract :
Unlike their hard real-time counterparts, soft real-time applications are only expected to guarantee their "expected delay" over input data space. This paradigm shift calls for customized statistical design techniques to replace the conventional pessimistic worst case analysis methodologies. We present a novel statistical time-budgeting algorithm to translate the application expected delay constraint into its components\´ local delay constraints. We utilize the mathematical properties of the problem to quickly calculate the system expected delay and incrementally estimate the component utility variation with its timing relaxation. Our algorithm determines the optimal maximum weighted timing relaxation of an application under expected delay constraint. Experimental results on core-based synthesis of several multimedia applications targeting field-programmable gate arrays show that our technique always improves the design area. Furthermore, it consistently outperforms optimal time budgeting under hard real-time constraint, which is the best existing competitor. Design area improvements were up to 26% and averaged about 17% on several MediaBench applications
Keywords :
field programmable gate arrays; high level synthesis; logic design; statistical analysis; component utility variation; core-based synthesis; expected delay constraint; field-programmable gate arrays; high-level synthesis; optimal maximum weighted timing relaxation; probabilistic analysis; probabilistic delay budget assignment; soft real-time applications; statistical design techniques; statistical time-budgeting algorithm; Algorithm design and analysis; Application software; Delay estimation; Delay systems; Design optimization; Field programmable gate arrays; Financial management; Performance analysis; Power system management; Timing; Expected delay constraint; high-level synthesis; probabilistic analysis; timing relaxation;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2006.878472