DocumentCode
1065254
Title
Test enrichment for path delay faults using multiple sets of target faults
Author
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume
22
Issue
1
fYear
2003
fDate
1/1/2003 12:00:00 AM
Firstpage
82
Lastpage
90
Abstract
Test sets for path delay faults in circuits with large numbers of paths are typically generated for path delay faults associated with the longest circuit paths. It is shown that such test sets may not detect faults associated with the next-to-longest paths. This may lead to undetected failures since shorter paths may fail without any of the longest paths failing. In addition, paths that appear to be shorter may actually be longer than the longest paths if the procedure used for estimating path length is inaccurate. A test enrichment procedure is proposed that increases significantly the number of faults associated with the next-to-longest paths that are detected by a test set without increasing its size. This is achieved by targeting both types of faults, but ensuring that the test generation procedure would detect the faults associated with the longest paths, while allowing the procedure the flexibility of detecting or not detecting the faults associated with the next-to-longest paths. The proposed procedure thus improves the quality of the test set without increasing its size. The test enrichment procedure is built on top of a new and effective dynamic test compaction procedure in order to demonstrate that test enrichment is effective even for compact test sets.
Keywords
automatic testing; circuit analysis computing; combinational circuits; delays; fault diagnosis; integrated circuit testing; logic testing; dynamic test compaction; path delay faults; test enrichment procedure; test generation; test generation procedure; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Compaction; Delay; Design automation; Electrical fault detection; Fault detection; Helium;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2002.805726
Filename
1158255
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