DocumentCode :
1066197
Title :
A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- 
m CMOS
Author :
Lee, Chihun ; Cho, Lan-Chou ; Wu, Jia-Hao ; Liu, Shen-Iuan
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
Volume :
55
Issue :
5
fYear :
2008
fDate :
5/1/2008 12:00:00 AM
Firstpage :
404
Lastpage :
408
Abstract :
A 50.8-53-GHz clock generator with a quadruplicate-harmonic-locked phase detector (PD) is presented to achieve a low spur and a low reference frequency. The proposed quadruplicate-harmonic-locked PD, a low-voltage Colpitts voltage-controlled oscillator, and a wide-range divide-by-2 divider are also presented. This clock generator has been fabricated in a 0.13-mum process. The measured reference spur is -59.88 dBc at 51.02 GHz with an input reference frequency of 199.3 MHz. The area is 0.93 mm times 1 mm with the on-chip loop filter and pads. It dissipates 87 mW without buffers from a 1.5-V supply.
Keywords :
CMOS digital integrated circuits; clocks; frequency dividers; millimetre wave oscillators; phase detectors; voltage-controlled oscillators; 0.13-mum CMOS process; Colpitts voltage-controlled oscillator; clock generator; divide-by-2 divider; frequency 50.8 GHz to 53 GHz; on-chip loop filter; quadruplicate-harmonic-locked phase detector; size 0.13 mum; voltage 1.5 V; Clock generator; phase detector; reference spur; voltage-controlled oscillator (VCO);
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2007.914430
Filename :
4450591
Link To Document :
