Title :
A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC
Author :
Tanabe, Akira ; Nakahara, Yasushi ; Furukawa, Akio ; Mogami, Tohru
Author_Institution :
NEC Corp., Kanagawa, Japan
fDate :
1/1/2003 12:00:00 AM
Abstract :
A redundant multivalued logic is proposed for high-speed communication ICs. In this logic, serial binary data are received and converted into parallel redundant multivalued data. Then they are restored into parallel binary data. Because of the multivalued data conversion, this logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was fabricated using a 0.18-μm CMOS process. The IC achieved an operating speed of 10 Gb/s with a supply voltage of only 1.3 V and with power consumption of 38 mW. This logic may achieve CMOS communication ICs with an operating speed several times greater than 10 Gb/s.
Keywords :
CMOS logic circuits; demultiplexing equipment; high-speed integrated circuits; low-power electronics; multivalued logic circuits; optical receivers; redundancy; 0.18 micron; 1.3 V; 10 Gbit/s; 38 mW; CMOS demultiplexer IC; high-speed communication ICs; multivalued data conversion; operating speeds; optical communication; parallel redundant multivalued data; power consumption; redundant multivalued logic; serial binary data; CMOS integrated circuits; CMOS logic circuits; CMOS technology; Clocks; Data conversion; Flip-flops; Frequency; MOSFETs; Multivalued logic; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2002.806287
