Title :
A Steep-Slope Tunnel FET Based SAR Analog-to-Digital Converter
Author :
Moon Seok Kim ; Huichu Liu ; Xueqing Li ; Datta, Soupayan ; Narayanan, Vijaykrishnan
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
This paper explores the energy efficiency advantage of a 6-bit III-V heterojunction tunnel field-effect transistor (HTFET) based successive-approximation register (SAR) analog-to-digital converter (ADC) with 20-nm gate length. Compared with the Silicon FinFET (Si FinFET) ADC, the HTFET SAR ADC achieves approximately 3 times power consumption reduction and 6 times size reduction. Signal-to-noise and distortion ratio is 31.4 dB for the HTFET SAR ADC, which is 2.81 dB higher than the Si FinFET ADC due to the decreased quantization noise rising from the high ON-current characteristic of HTFET at low supply voltage. The energy per conversion step for both HTFET and Si FinFET ADC designs are 0.43 and 1.65 fJ/conversion-step, respectively, at a fixed supply voltage of 0.30 V.
Keywords :
III-V semiconductors; analogue-digital conversion; electron device noise; flip-flops; high electron mobility transistors; integrated circuit design; logic design; low-power electronics; power consumption; silicon; tunnel transistors; HTFET SAR ADC; III-V heterojunction tunnel field-effect transistor; SAR analog-to-digital converter; Si; distortion ratio; power consumption reduction; quantization noise; signal-to-noise ratio; silicon FinFET ADC; size 20 nm; steep-slope tunnel FET; successive-approximation register; supply voltage; voltage 0.30 V; CMOS integrated circuits; FinFETs; Integrated circuit modeling; Logic gates; Noise; Silicon; Analog-to-digital converter (ADC); heterojunction tunnel FET (HTFET); successive-approximation register (SAR); ultra-low-power; ultra-low-power.;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2014.2359663
