A 1.76-GHz 22.6-mW ΔΣ fractional-n frequency synthesizer

Author

Ahola, Rami ; Halonen, Kari

Author_Institution

Electron. Circuit Design Lab., Helsinki, Finland

Volume

38

Issue

1

fYear

2003

fDate

1/1/2003 12:00:00 AM

Firstpage

138

Lastpage

140

Abstract

A ΔΣ fractional-N frequency synthesizer for the 2-GHz-range wireless communication applications is implemented in a 0.35-μm BiCMOS process, using only CMOS components. The synthesizer achieves a close-in phase noise of -81 dBc/Hz, while the spurious tones are at -85 dBc. The synthesizer features a multiple-modulus prescaler employing the phase-switching architecture to minimize the power dissipation. The entire prescaler, including the gigahertz-speed first stages, is implemented using full-swing logic. The current source structure employed in the charge pump provides a constant output current over a wide, almost rail-to-rail output voltage range. The power dissipation of the synthesizer chip is 22.6 mW from a 2.7-V supply.

Keywords

BiCMOS integrated circuits; UHF integrated circuits; frequency synthesizers; mixed analogue-digital integrated circuits; prescalers; radio equipment; ΔΣ fractional-n frequency synthesizer; 0.35 micron; 1.76 GHz; 2 GHz; 2.7 V; 22.6 mW; BiCMOS process; CMOS components; charge pump; constant output current; current source structure; delta-sigma frequency synthesizer; full-swing logic; gigahertz-speed first stages; multiple-modulus prescaler; phase noise; phase-switching architecture; rail-to-rail output voltage range; wireless communication applications; BiCMOS integrated circuits; CMOS logic circuits; CMOS process; Charge pumps; Frequency synthesizers; Phase noise; Power dissipation; Rail to rail outputs; Voltage; Wireless communication;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.806261

Filename

1158792