Title :
Minimum memory buffers in DSP applications
Author :
Ade, M. ; Lauwereins, Rudy ; Peperstraete, J.A.
Author_Institution :
ESAT, Katholieke Univ., Leuven, Heverlee
fDate :
3/17/1994 12:00:00 AM
Abstract :
The authors compute the minimum required buffer sizes that still guarantee the construction of a deadlock-free static schedule in synchronous multirate data flow graphs. The results are applicable to the rapid prototyping of DSP algorithms
Keywords :
buffer storage; digital signal processing chips; directed graphs; logic arrays; memory architecture; scheduling; DSP algorithms; FIFO buffer; FPGA area; deadlock-free static schedule; minimum memory buffers; minimum required buffer sizes; multirate signal processing; rapid prototyping; synchronous multirate data flow graphs;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19940360
