DocumentCode
1067153
Title
Very high speed continuous sampling using matched delays
Author
Liu, Wenxin ; Kang, Jiawen ; Cavin, R.K.
Volume
30
Issue
6
fYear
1994
fDate
3/17/1994 12:00:00 AM
Firstpage
463
Lastpage
465
Abstract
The authors describe a scheme for very high speed continuous sampling of digital data. It is based on a high speed noncontinuous sampling device that uses matched data and clock delay lines. The frequency of the sample clock necessary for continuous sampling is derived, and the components needed to deskew and synchronise the latch outputs for storage in an output register are detailed
Keywords
CMOS integrated circuits; clocks; data acquisition; delay circuits; digital integrated circuits; sampled data systems; synchronisation; CMOS circuit; clock delay lines; clock recovery circuit; digital data sampling; high speed noncontinuous sampling device; latch output deskewing; latch output synchronisation; matched delays; output register storage; sample clock frequency; very high speed continuous sampling;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19940339
Filename
280569
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