• DocumentCode
    1067319
  • Title

    Vector algorithm for Reed-Muller expansions

  • Author

    Clarkson, T.G. ; Zhuang, N.

  • Author_Institution
    Dept. of Electron. & Electr. Eng., King´s Coll., London
  • Volume
    30
  • Issue
    7
  • fYear
    1994
  • fDate
    3/31/1994 12:00:00 AM
  • Firstpage
    549
  • Lastpage
    550
  • Abstract
    A novel vector algorithm for Reed-Muller (RM) expansions is proposed which can save as many as a factor of 2n-1 memory elements compared with previous matrix algorithms
  • Keywords
    VLSI; logic arrays; logic gates; Reed-Muller expansions; VLSI; logic circuits; memory elements; vector algorithm;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19940389
  • Filename
    280590
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1067319