DocumentCode
106737
Title
BCH Code Selection and Iterative Decoding for BCH and LDPC Concatenated Coding System
Author
Pin-Han Chen ; Jian-Jia Weng ; Chung-Hsuan Wang ; Po-Ning Chen
Author_Institution
Dept. of Electr. & Comput. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume
17
Issue
5
fYear
2013
fDate
May-13
Firstpage
980
Lastpage
983
Abstract
In this letter, we consider a concatenated BCH and QC-LDPC coding system for potential use of data protection on flash memory. Two issues are studied, and strategies to resolve them are proposed. First, in order to guarantee that the concatenated coding system is free from undesired error floor, we propose a strategy to select the outer BCH codes according to the error patterns of inner QC-LDPC code. We next present an iterative decoding algorithm between inner QC-LDPC and outer BCH codes to alleviate the performance degradation in the waterfall region due to code-concatenation rate loss. The two proposals jointly provide a feasible design for the concatenated BCH and QC-LDPC coding system. Simulations to verify the performance of the proposed concatenated coding system design are given at the end.
Keywords
BCH codes; concatenated codes; iterative decoding; parity check codes; BCH code selection; LDPC concatenated coding system; QC-LDPC coding system; code-concatenation rate loss; concatenated BCH coding system; concatenated coding system design; data protection; error patterns; flash memory; iterative decoding; iterative decoding algorithm; performance degradation; undesired error floor; Ash; Bit error rate; Charge carrier processes; Decoding; Encoding; Iterative decoding; Concatenated coding; flash memory; iterative decoding;
fLanguage
English
Journal_Title
Communications Letters, IEEE
Publisher
ieee
ISSN
1089-7798
Type
jour
DOI
10.1109/LCOMM.2013.031913.130142
Filename
6486533
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