DocumentCode
106742
Title
A GPU Implementation of a MAP Decoder for Synchronization Error Correcting Codes
Author
Briffa, J.A.
Author_Institution
Dept. of Comput., Univ. of Surrey, Guildford, UK
Volume
17
Issue
5
fYear
2013
fDate
May-13
Firstpage
996
Lastpage
999
Abstract
In this paper we present a parallel implementation of a MAP decoder for synchronization error correcting codes. For a modest implementation effort, we demonstrate a considerable decoding speedup, up to two orders of magnitude even on consumer GPUs. This enables the analysis of much larger codes and worse channel conditions than previously possible, and makes applications of such codes feasible for software implementations.
Keywords
channel coding; error correction codes; graphics processing units; maximum likelihood decoding; GPU implementation; MAP decoder parallel implementation; channel conditions; software implementations; synchronization error correcting codes; Complexity theory; Decoding; Graphics processing units; Instruction sets; Kernel; Synchronization; CUDA; GPU; Insertion-deletion correction; MAP decoder; forward-backward algorithm;
fLanguage
English
Journal_Title
Communications Letters, IEEE
Publisher
ieee
ISSN
1089-7798
Type
jour
DOI
10.1109/LCOMM.2013.031913.130203
Filename
6486534
Link To Document