The gated-access MNOS memory transistor

A new modification of the MNOS transistor results in significant advantages. It combines a depletion-mode channel with electrically separate electrodes over the memory portion and the fixed threshold portion of a step-gate device. This elimnates read disturb during interrogation; therefore, much longer retention is now possible. It also decreases access time within an LSI array. For block-written EAROM´s, a new form of dynamic inhibit makes memory array isolation unnecessary. These and other improvements obtained with this structure do not require new processes or a significant increase in size.