Systolic architecture for inverse discrete cosine transform

The authors present an algorithm and its systolic implementation for computing the 1-D N-point inverse discrete cosine transform (IDCT), where N is a power of two. The architecture requires (N²-1)/3 multipliers and can evaluate one N-point IDCT every clock cycle. Owing to the features of regularity and modularity, the architecture is well suited to VLSI implementation. Compared with existing related arrays, the proposed algorithm has a better area-time performance. In addition, it can be extended to implementing the 2-D IDCT based on the row-column decomposition method