On routability for FPGAs under faulty conditions

The field programmable gate array (FPGA) routing resources are fixed and their usage is constrained by the location of programmable interconnects (PIs) such as antifuses. The routing or the interconnect delays are determined by the length of segments assigned to the nets of various lengths and the number of PIs programmed for routing of each net. Due to the use of PIs certain unconventional faults may appear. In this paper we model the PI faults and address the design and routability of the FPGA channel architecture to achieve 100% routing with minimum performance penalty in the presence of PI faults. A channel routing algorithm has also been developed which routes nets in the presence of PI faults. Experiments were performed by randomly injecting faults of different types into the routing channel and then using the routing algorithm to determine the routability of the synthesized architecture. Results on a set of industrial designs and MCNC benchmark examples show the feasibility of achieving routability with minimum performance penalty when a large number of faults are present in the channel