DocumentCode :
1068044
Title :
Processor architecture and data buffering
Author :
Mulder, Hans ; Flynn, Michael J.
Author_Institution :
Dept. of Electr. Eng., Delft Univ., Netherlands
Volume :
41
Issue :
10
fYear :
1992
fDate :
10/1/1992 12:00:00 AM
Firstpage :
1211
Lastpage :
1222
Abstract :
The tradeoff between visualizing or hiding the highest levels of the memory hierarchy, which impacts both performance and scalability, is examined by comparing a set of architectures from three major architecture families: stack, register, and memory-to-memory. The stack architecture is used as reference. It is shown that scalable architectures require at least 32 words of local memory and therefore are not applicable for low-density technologies. It is also shown that software support can bridge the performance gap between scalable and nonscalable architectures. A register architecture with 32 words of local storage allocated interprocedurally outperforms scalable architectures with equal sized local memories and even some with larger sized local memories. When a small cache is added to an unscalable architecture, their performance advantage becomes significant
Keywords :
buffer storage; computer architecture; data structures; data buffering; memory hierarchy; memory-to-memory; performance; register; scalability; software support; stack; Bridges; Computer architecture; Computer buffers; Costs; Data visualization; Memory architecture; NASA; Registers; Scalability; Software performance;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.166600
Filename :
166600
Link To Document :
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