Very low power consumption Viterbi decoder LSIC employing the SST (scarce state transition) scheme for multimedia mobile communications

Author

Seki, Katsuyuki ; Kubota, Sho ; Mizoguchi, Masato ; Kato, Shigeo

Author_Institution

NTT Radio Commun. Syst. Labs., Kanagawa

Volume

30

Issue

8

fYear

1994

fDate

4/14/1994 12:00:00 AM

Firstpage

637

Lastpage

639

Abstract

A very low power consumption Viterbi decoder LSIC has been developed by using a low supply voltage 0.8 μm CMOS masterslice process technology. By employing the scarce state transition (SST) scheme, this LSIC achieves a drastic reduction in power consumption below 600 μW at a supply voltage of 1 V when the data rate is 1152 kbit/s and the bit error rate is less than 10^-3. This excellent performance has paved the way to employing the strong forward error correction and low power consumption portable terminals for personal communications, mobile multimedia communications, and digital and audio broadcasting

Keywords

CMOS integrated circuits; decoding; digital integrated circuits; digital radio systems; error correction; error statistics; large scale integration; mobile radio systems; multimedia systems; 0.8 micron; 1 V; 1152 kbit/s; 600 muW; BER; CMOS masterslice process technology; Viterbi decoder LSI; audio broadcasting; bit error rate; digital broadcasting; forward error correction; low power consumption; multimedia mobile communications; personal communications; portable terminals; scarce state transition;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:19940460

Filename

280654