• DocumentCode
    1068168
  • Title

    Single-precision multiplier with reduced circuit complexity for signal processing applications

  • Author

    Lim, Y.C.

  • Author_Institution
    Dept. of Electr. Eng., Nat. Univ. of Singapore, Singapore
  • Volume
    41
  • Issue
    10
  • fYear
    1992
  • fDate
    10/1/1992 12:00:00 AM
  • Firstpage
    1333
  • Lastpage
    1336
  • Abstract
    When two numbers are multiplied, a double-wordlength product is produced. In applications where only the single-precision product is required, the double-wordlength result is rounded to single-precision. Hence, in single-precision applications, it is not necessary to compute the least significant part of the product exactly. Instead, it is only necessary to estimate the carries generated in the computation of the least significant part that will ripple into the most significant part of the product. This will produce a single-precision multiplier with significantly reduced circuit complexity. Three novel methods for realizing this class of reduced complexity single-precision multipliers are introduced and their performance analyzed
  • Keywords
    digital arithmetic; multiplying circuits; signal processing; reduced circuit complexity; signal processing applications; single precision multiplier; Complexity theory; Convolution; Digital arithmetic; Encoding; Error analysis; Performance analysis; Polynomials; Signal processing; Systolic arrays; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.166611
  • Filename
    166611