A 120-MHz BiCMOS superscalar RISC processor

Author

Tanaka, Shigeya ; Hotta, Takashi ; Murabayashi, Fumio ; Yamada, Hiromichi ; Yoshida, Shoji ; Shimamura, Kotaro ; Katsura, Koyo ; Bandoh, Tadaaki ; Ikeda, Koichi ; Matsubara, Kenji ; Saitou, Kouji ; Nakano, Tetsuo ; Shimizu, Teruhisa ; Satomura, Ryuichi

Author_Institution

Res. Lab., Hitachi Ltd., Ibaraki, Japan

Volume

29

Issue

4

fYear

1994

fDate

4/1/1994 12:00:00 AM

Firstpage

389

Lastpage

396

Abstract

A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm×16.5 mm, and utilizes 3.3 V/0.5 μm BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design

Keywords

BiCMOS integrated circuits; VLSI; microprocessor chips; parallel architectures; pipeline processing; reduced instruction set computing; 0.5 micron; 120 MHz; 240 MFLOPS; 240 MIPS; 3.3 V; BiCMOS technology; VLSI; instruction cache; superscalar RISC processor; tag bit; BiCMOS integrated circuits; CMOS technology; Clocks; Integrated circuit technology; Microarchitecture; Performance gain; Pipelines; Process design; Processor scheduling; Reduced instruction set computing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.280686

Filename

280686