A fuzzy logic inference processor

Author

Fattaruso, John W. ; Mahant-Shetti, Shivaling S. ; Barton, Brock J.

Author_Institution

Integrated Syst. Lab., Texas Instrum. Inc., Dallas, TX, USA

Volume

Issue

fYear

1994

fDate

4/1/1994 12:00:00 AM

Firstpage

397

Lastpage

402

Abstract

A mixed analog-digital fuzzy logic inference engine chip fabricated in an 0.8 μm CMOS process is described. Interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules, including a center-of-mass defuzzification, may be computed in 2 μs

Keywords

CMOS integrated circuits; fuzzy logic; inference mechanisms; integrated logic circuits; microprocessor chips; mixed analogue-digital integrated circuits; 0.8 micron; 2 mus; CMOS process; analog charge-domain circuits; center-of-mass defuzzification; fuzzy logic inference processor; mixed analog-digital chip; Analog computers; Analog-digital conversion; CMOS process; Computer interfaces; Concurrent computing; Engines; Fuzzy logic; Logic arrays; Random access memory; Read-write memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.280687

Filename

280687

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1068347