A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers

Author

Ishibashi, Koichiro ; Komiyaji, Kunihiro ; Morita, Sadayuki ; Aoto, Toshiro ; Ikeda, Shuji ; Asayama, Kyoichiro ; Koike, Atsuyosi ; Yamanaka, Toshiaki ; Hashimoto, Naotaka ; Iida, Haruhito ; Kojima, Fumio ; Motohashi, Koichi ; Sasaki, Katsuro

Author_Institution

Central Res. Lab., Hitachi Ltd, Tokyo, Japan

Volume

29

Issue

4

fYear

1994

fDate

4/1/1994 12:00:00 AM

Firstpage

411

Lastpage

418

Abstract

A 16-Mb CMOS SRAM using 0.4-μm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm² is fabricated and an address access time of 12.5 ns has been achieved

Keywords

CMOS integrated circuits; SRAM chips; circuit layout; redundancy; 0.4 micron; 12.5 ns; 16 Mbit; CMOS SRAM; address access time; common-centroid-geometry-layout; igh soft-error immunity; memory cell; redundancy technique; sense amplifiers; stacked capacitors; CMOS technology; Cache memory; Capacitors; Circuit simulation; Costs; Delay effects; Random access memory; Redundancy; Supercomputers; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.280689

Filename

280689