A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates

Author

Iwabuchi, Masato ; Usami, Masami ; Kashiyama, Masamori ; Oomori, Takashi ; Murata, Shigeharu ; Hiramoto, Toshiro ; Hashimoto, Takashi ; Nakajima, Yasuhiro

Author_Institution

Device Dev. Center, Hitachi Ltd, Tokyo, Japan

Volume

29

Issue

4

fYear

1994

fDate

4/1/1994 12:00:00 AM

Firstpage

419

Lastpage

425

Abstract

An 18-kb RAM with 9-kgate control logic gates operating during a cycle-time of 1.5 ns has been developed. A pseudo-dual-port RAM function is achieved by a two-bank structure and on-chip control logic. Each bank can operate individually with different address synchronizing the single clock. A sense-amplifier with a selector function reduces the reading propagation time. Bonded SOI wafers reduce the memory-cell capacitance, and this results in a fast write cycle without sacrificing α-particle immunity. The chip is fabricated in a double polysilicon self-aligned bipolar process using trench isolation. The minimum emitter size is 0.5×2 μm² and the chip size is 11×11 mm²

Keywords

bipolar integrated circuits; integrated circuit technology; integrated memory circuits; multiport networks; random-access storage; semiconductor-insulator boundaries; silicon; 1.5 ns; 18 kbit; bonded SOI wafers; chip size; control logic gates; double polysilicon self-aligned bipolar process; memory-cell capacitance; minimum emitter size; on-chip control logic; pseudo-dual-port RAM; reading propagation time; selector function; sense-amplifier; trench isolation; two-bank structure; write cycle; Circuits; Clocks; Logic devices; Logic gates; Pulse generation; Random access memory; Read-write memory; Signal generators; Space vector pulse width modulation; Wafer bonding;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.280690

Filename

280690