250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture

Author

Takai, Yasuhiro ; Nagase, Mamoru ; Kitamura, Mamoru ; Koshikawa, Yasuji ; Yoshida, Naoyuki ; Kobayashi, Yasuaki ; Obara, Takashi ; Fukuzo, Yukio ; Watanab, Hiroshi

Author_Institution

LSI Memory Div., NEC Corp., Kanagawa, Japan

Volume

29

Issue

4

fYear

1994

fDate

4/1/1994 12:00:00 AM

Firstpage

426

Lastpage

431

Abstract

A 3.3-V 512-k×18-b×2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 113.7-mm², which is the same die size as the conventional DRAM, has been achieved with 0.50-μm CMOS process technology

Keywords

CMOS integrated circuits; DRAM chips; memory architecture; 0.50 micron; 250 Mbyte/s; 3.3 V; CMOS process technology; GTL interface; SDRAM; address-access path; column switch; data-out buffer; die size; latch circuits; synchronous DRAM; three-stage pipelined architecture; CMOS process; CMOS technology; Circuits; Clocks; Decoding; Microprocessors; National electric code; Random access memory; SDRAM; Switches;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.280691

Filename

280691