A 40-mW 55 Mb/s CMOS equalizer for use in magnetic storage read channels

Author

Pai, Patrick K D ; Abidi, Asad A.

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

29

Issue

4

fYear

1994

fDate

4/1/1994 12:00:00 AM

Firstpage

489

Lastpage

499

Abstract

A monolithic active equalizer in 2-μm CMOS technology is described, suitable for use in magnetic storage read channels employing peak-detection. Computer simulation of the channel and numerical optimization of equalizer performance have led to a 4-pole equalizer which outperforms conventional 7-pole linear-phase pulse-slimming equalizers. Circuits with matched and scaled stray capacitances use low transconductance amplifiers, with a total on-chip power dissipation of 40 mW (excluding output buffers). A master-slave architecture tunes filter pole frequencies and quality factors (Q) to their nominal values against process and temperature variations

Keywords

CMOS integrated circuits; equalisers; magnetic disc storage; mixed analogue-digital integrated circuits; 2 micron; 4-pole equalizer; 40 mW; 55 Mbit/s; CMOS equalizer; filter pole frequencies; low transconductance amplifiers; magnetic storage read channels; master-slave architecture; monolithic active equalizer; numerical optimization; peak-detection; quality factors; scaled stray capacitances; CMOS technology; Capacitance; Circuits; Computer simulation; Equalizers; Magnetic memory; Master-slave; Power dissipation; Pulse amplifiers; Transconductance;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.280699

Filename

280699