A fully digitally programmable CNN chip

Author

Sargeni, Fausto ; Bonaiuto, Vincenzo

Author_Institution

Dept. of Electron. Eng., Tor Vergata Univ., Rome, Italy

Volume

42

Issue

11

fYear

1995

fDate

11/1/1995 12:00:00 AM

Firstpage

741

Lastpage

745

Abstract

The successful development of cellular neural networks is dependent on hardware implementation. This letter presents a VLSI implementation of a multichip-oriented, fully programmable, 3×3 digitally programmable cellular neural network (DPCNN). This chip covers most of the available one-neighborhood templates for image processing applications. Moreover, it can be easily interconnected to others to carry out very large CNN arrays

Keywords

CMOS integrated circuits; analogue processing circuits; cellular neural nets; image processing; mixed analogue-digital integrated circuits; neural chips; CMOS process; VLSI implementation; cellular neural networks; current mode implementation; digitally programmable CNN chip; image processing; interconnection; multichip-oriented fully programmable CNN; one-neighborhood templates; very large CNN arrays; Cellular neural networks; Frequency; Image processing; Integrated circuit interconnections; Neural network hardware; Operational amplifiers; Prototypes; Solid state circuits; Transconductance; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.475256

Filename

475256