Three-dimensional capacitance computations for VLSI/ULSI interconnections

Three-dimensional simulations of metallization wires of VLSI/ULSI interconnections that are plagued with unreasonably large memory requirements and execution times are discussed. A strategy is presented for overcoming these problems. A principal feature is the use of a domain contraction technique, which accounts for the fringing electric field throughout the infinite domain above and below the levels where the wires appear and provides a major reduction in the number of nodal points for a finite-difference computation. Moreover, an iterative method (successive over-relaxation) is used to alleviate memory requirements, a nonuniformly distributed nodal array is used to reduce the number of nodal points still further, and parallel processing is used to reduce execution time. It is argued that rounded edges and corners for the simulation of the wires are the only appropriate configurations at current levels of miniaturization. This avoids the problem of electric-field singularities at sharp edges and corners and results in significantly reduced capacitance coefficients