Analysis of GaAs FET´s for integrated logic

This paper presents an analysis of the speed and power dissipation of various GaAs FET inverter circuits as prototypes of integrated logic circuit design. The analysis provides analytical expressions to assess the switching performance of enhancement-mode and depletion-mode MESFET´s and JFET´s with respect to switching-speed and power-dissipation capabilities in optimized configurations. Various load elements are described and analyzed for circuit applications. The various logic gates, now under development, are compared in their switching performance and a review of the state of the art is given. Prospects of large-scale integration (LSI) of gigabit logic for GaAs FET´s are assessed.