Title :
Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme
Author :
Song Jia ; Shilin Yan ; Yuan Wang ; Ganggang Zhang
Author_Institution :
Key Lab. of Microelectron. Devices & Circuits, Peking Univ., Beijing, China
Abstract :
A new design scheme intended to improve the performance of true single-phase clocked (TSPC) dual modulus prescalers is presented. Two branches of TSPC D flip-flops are merged to reduce both power and device count. An HSPICE simulation of the proposed scheme demonstrates the highest power efficiency and best power-delay product among the referenced designs.
Keywords :
circuit simulation; flip-flops; high-speed integrated circuits; logic design; logic gates; low-power electronics; HSPICE simulation; TSPC D flip-flops; branch-merged true single-phase clocked scheme; low-power high-speed dual modulus prescalers; power efficiency; power-delay product;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2014.4146
