Title :
A hybrid wave pipelined network router
Author :
Nyathi, Jabulani ; Delgado-Frias, José G.
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
fDate :
12/1/2002 12:00:00 AM
Abstract :
In this paper, a novel hybrid wave pipelined bit-pattern associative router (BPAR) is presented. A router is an important component in communication network systems. The BPAR allows for flexibility and can accommodate a large number of routing algorithms. In this study, a hybrid wave pipelined approach has been proposed and implemented. Hybrid wave pipelining allows for the reduction of the delay difference between the maximum and minimum delays by narrowing the gap between each stage of the system. This approach yields narrow "computing cones" that could allow faster clocks to be run. This is the first study in wave pipelining that deals with a system that has substantially different pipeline stages. The BPAR has three stages: condition match, selection function, and port assignment. In each stage, data delay paths are tightly controlled in order to optimize the proper propagation of signals. Internal control signals are generated to ensure that data propagates between stages in a proper fashion. Results from our study show that using a hybrid wave pipelining significantly reduces the clock period. The hybrid wave pipelined system described in this paper has been fabricated using a 0.5-μm technology.
Keywords :
CMOS digital integrated circuits; VLSI; clocks; content-addressable storage; delays; pipeline processing; telecommunication network routing; timing; 0.5 micron; CMOS circuit; bit-pattern associative memory; clock period reduction; communication network systems; computer network address decoder; computing cones; condition match; data delay paths; delay balancing; delay difference reduction; dynamic ternary content addressable memory; hybrid wave pipelined VLSI router; hybrid wave pipelined bit-pattern associative router; internal control signals; maximum delays; minimum delays; port assignment; routing algorithms; selection function; signal propagation optimization; wave pipelined clock; Associative memory; Clocks; Communication networks; Delay effects; Network topology; Pipeline processing; Propagation delay; Routing; Signal generators; Table lookup;
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
DOI :
10.1109/TCSI.2002.805705
