Single 5-V, 64K RAM with scaled-down MOS structure

A single 5-V, 64K RAM was designed and fabricated using double poly-Si and 3-µm process technologies. The design features of this dynamic RAM are described. In particular, memory-cell layout and the on-chip bias generator are designed to realize a marginal single 5-V RAM. The fabricated device provides a typical access time of 120 ns and an operating power of 170 mW. Extensive measurements of the 64K RAM and studies of scaled devices are presented. In line with these studies, scaling of RAM performances is discussed in terms of a scaled-down process and power-supply voltage.