Title :
A dense gate matrix layout method for MOS VLSI
Author :
Lopez, Alexander D. ; Law, Hung-Fai S.
Author_Institution :
Bell Laboratories, Murray Hill, NJ
fDate :
8/1/1980 12:00:00 AM
Abstract :
A rapid and systematic method for performing chip layout of VLSI circuits is described. This method utilizes the configuration of a matrix composed of intersecting rows and columns to provide transistor placement and interconnections. This structure, which is orderly and regular, gives high device-packing density and allows ease of checking for layout errors. Resulting layouts may be updated to new design rules automatically. This method has been used in the layout of a 20 000-transistor section of a VLSI circuit.
Keywords :
Circuit topology; Computational geometry; Conductors; Costs; Design automation; Integrated circuit interconnections; Logic design; Silicon; Very large scale integration; Wiring;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1980.20086
